RPC Crate Controller board v4.0.

 Introduction
 Front panel Connectors
 VME back plane
 Schematics of the board (all files in ps format)
 Parts list
 Power dissipation

Introduction.

RPC crate Controller board is designed to download, control and readout the RPC Readout Boards. RPC Crate Controller interfaces the String Controller to the VME back plane. IN case of shift register readout it will read the data upon arrival corresponding command from up to 20 readout boards located in the same VME Crate, sparcify data and store it in FIFO memory, and then on the request of the String Controller write it out through RS-485 OUT interface. It is also designed for future possible expansion to control RPC Tester Board and Bubbler Controller board. It has two 34 pin RS-485 interface on the front edge to connect to the String controller. 16 Pin ECL input for trigger information and spare 8 pin ECL output which can be used for debugging purposes. This board incorporates programmable gate array Xilinx4013 which will provide flexible tool for controlling and modifying readout process. 3 bit address will allow string of up to the 8 Crate Controller Boards on the same cable controlled by one String Controller Board. 4096x16 bit FIFO memory provide enough storage place to accommodate 2 full worse case hit (calculated by 20 boards (max crate capacity) got all 96 channels hits) Typical event will have about 100 hits so after sparcification we will be able to allocate up to 40 hit events in FIFO memory. Programmable digital delay line will give flexible and easily adjustable delay for synchronization clock signals for all crates. Each Crate Controller Board will have their own onboard 60MHz clock. It will allow to process data obtained from the RPC Readout Boards much faster then using clock provided by String Controller through RS-485 line. It will allow to minimize the time required for data sparcification and diminish the total readout time which will be limited by back plane capacity and transmission speed over RS-485 lines.
 

VME backplane can not handle  clock faster than 10 MHZ. Given that in current design each Readout board required at least 26 commands to read the information from it and given that max number of boards in the crate is 20, the max. speed of reading out entire crate is 10 MHz/26/20/2=10KHz. Taking into account that typical event will have around 100 hits over 20 readout boards, after sparsification we will need to transmit 100*10 000=1M16 bit words per second over RS-485 lines. Maximum operating rate for RS-485 is 15 Mb/s, having 8 Crate controllers in one string, it`s quite feasible to handle 1Mb from each crate. So it will leave us with 10KHz maximum readout rate limited by both VME back plane and RS-485 interface.

 

Front panel connectors.

On the front panel located four connectors. Two RS-485 and two ECL input outputs. RS-485 consists of two 34 pin connectors. Pin out description is given below.  All connectors on the front edge of the board have pin 1 on the bottom right side. Pin 1 has positive polarity for all differential inputs and outputs. Pin numbering as well as connector polarity are shown on the board silk-screen. I will use standard notation for Xilinx pin out, which include the name of the pin and if the pin name does not include pin number I'll provide it in parentheses.
RS-485
RS-485 requires proper termination. The first and the last receiver/transmitter in the line should have 120 Ohm terminating resistor. String controller by default should always be at one end of transmission line, while Crate Controller has optional termination reasistor. So care should be taken about the last in the string Crate Controller, It should have installed 6 8sip packages 120 Ohm resistors (R22, R23, R24. R25, R29, R30, R31, R32) and all other Crate Controllers in the string should have none of them.  In order to get the best performance all Crate controllers should be attached to the string Star configuration will degrade transmission performance sagnificantly.

RS_485 IN connector has 17 lines, 16 of which are inputs and line 17 is designated party line. Party line can be selected as read or write.
RS-485 OUT has also 17 lines, but 16 of which designated for output. Line 17 is selectable bidirectional line. Care should be taken about not allowing two simultaneous drivers on the same line.
 
 
RS-485 IN
RS-485 OUT.
Description Channel# Xilinx 4013 Pinout
GCLK 1 CCLK(119)and io112
DIN 2 din(io117)
PROG* 3 program*(82)
RUN 4 io50
MODE(1) 5 io37
MODE(2) 6 io43
MODE(3) 7 io36
MODE(4) 8 io35
MODE(5) 9 io33
SPARE1 10 io34
SPARE2 11 io31
READ 12 io32
Universal 13 io68
ADDR(1) 14 -(*)
ADDR(2) 15 -(*)
ADDR(3) 16 -(*)
Party Line 17 io30(**)
 (*) Decoded address after bit by bit comparison will go to the pin io67. 
(**) Party line also has two additional lines which controll direction: 
Read enable RE* io28 
Write enable WE io27
Description Channel# Xilinx 4013 Pinout
DATA(0) 1 io66
DATA(1) 2 io65
DATA(2) 3 io64
DATA(3) 4 io63
ADDR(0) 5 io62
ADDR(1) 6 init*_io59
ADDR(2) 7 io58
ADDR(3) 8 io57
ADDR(4) 9 io56
ADDR(5) 10 io55
ADDR(6) 11 io54
ADDR(7) 12 io53
ADDR(8) 13 io52
STATUS(0) 14 hdc_io44
STATUS(1) 15 io49
STATUS(2) 16 ldc_io48
SPARE IO 17 io45(*)
 (*) Spare IO line also has two additional lines which controll direction: 
Read enable RE* io47 
Write enable WE io46
RS-485 out enabled only when selected by Universal or Addr, the same is true for first for channels of RS-485 in (GCLK, DIN, PROG* and RUN). Whenever this commands are used they should issued together with Universal or Addr commands. 3 bits address specifier allows to choose one of eight Crate controller modules, while Universal allows to transmit commands to all available modules. GCLK line has dual puprpose, during configuration time it supplyes configuration clock for Xilinx (CCLK), after configuration it works as a regular Global Clock. This line is connected to CCLK input of Xilinx and standard io pin. After configuration time CCLK input of Xilinx can not be used, so for GCLK input we need different io pin.

First for signals GCLK, DIN, PROG* and RUN enabled by or Universal or ADDR signal. Three bit Address is decoded on the board using bit by bit comparator and dip switch selector. It makes possible up to 8 RPC controllers be controlled by one String Controller.

Party Line
RS-485 specify value of termination resistors 120Ohm, which allows data transmission over lines with characteristic impedance in range 100-120Ohm. In order to specify consistent Party line, line which will have certain level (positive) almost all the time and as soon as any module will require service it will change level to the opposite one (negative). In case of RS-485 all drivers have active high and active low states so straightforward use of them will cause contention. On our design party line has well define level while party Line driver is disabled (+280mV which garantee positive state acoording RS-485 standard high>200mv, low<-200mV). Transceiver controlling Party Line has three possible states
1. Read and Write on Party Line Disabled. Party Line has definite High Level
2. Write on Party Line Enabled. Party Line is driven Low.
3. Read on Party Line Enabled. Signal from Party Line goes to Xilinx.
In order to provide maximum communication speed over Party line it requires proper termination. The output impedance should be 120Ohm and as it was mentioned before drop over disabled output should be in range of 300mV. Choosing value of resistors 510, 130 and 510 we'll get output impedance 115 Ohm and default voltage swing 280mV.

Spare IO.
This Line can be used as input or output. Care should be taken about termination of the last transceiver in the string. 120Ohm termination resistor is connected through the jumper. In case of last transceiver it jumper should be on.

ECL
On the front edge this board also has 16 pin (8 channels) ECL input which can be used as input for testing RPC readout boards or as for trigger information. 8 pin ECL output is added only as spare one for testing purposes.
 
16 pin (8 channels) ECL
8 Pin ECL output 
Channel # Connector pinout Xilinx 4013 Pinout
1 1-2 io25
2 3-4 io26
3 5-6 io23
4 7-8 io24
5 9-10 io21
6 11-12 io22
7 13-14 io17
8 15-16 io18
 
Channel # Connector pinout Xilinx 4013 Pinout
1 1-2 io16
2 3-4 io15
3 5-6 io14
4 7-8 tms_io13
 
 

VME back plane.

Global Clock. In order to allow higher clock frequency we designated 4 Global Clock lines on the backplane. Even more each of this lines can be driven by two buffers sumultaneously (if jumpers JP1-4 are placed). Each RPC readout board in their turn has selectable Clock input line, which means that ne clock line will drive only 5 RPC readout boards (20 boards total crate capacity). It will decrease the capacitive load per driving clock buffer and will allow stable clock with frequency up to 10 MHz. In case if 74ls244 buffer will not be able to handle this frequency it should be replaced with 74f244 buffer.
 
 
 
Lines designated for RPC readout
Spare Lines for possible future expansions.
 
Signal 
Name		 Xilinx Pin VME 
Connector
DIN dout(118) C4
CCLK - C2
Prog* - C3
Run io109 C5
Addr1 io126 A1
Addr2 io125 A2
Addr3 io124 A3
Addr4 io123 A4
Addr5 io116 C1
Addr6 io115 C6
Addr7 io114 C7
Addr8 io113 C8
Mode1 io106 A8
Mode2 io107 A7
Mode3 io111 A6
Mode4 io108 A5
Global CLK io104 A27-A30
Tok-rtn io105 B10
 
Signal 
Name		 Xilinx Pin VME 
Conector
Addr0 io90 C23
Addr1 io89 C24
Addr2 io88 A24
Addr3 io87 C25
Addr4 io86 A25
Addr5 io85 C26
Addr6 io83 A26
Addr7 io78 C27
Data0 io103 C15
Data1 io102 C16
Data2 io99 C17
Data3 io98 C18
Data4 io97 C19
Data5 io96 C20
Data6 io95 C21
Data7 io94 C22
Data En* io92 -
W*_R io93 -
 
 

 Schematics of the board (all files in ps format)

if you want to get all schematic sheets alltogether I created file schematic.tar.gz (334k). After you download this file you have to gunzip and untar it: Often web browser unzip the file for you, so if this is the case you will only need to untar it.

Parts list

Below are given all parts used on Crate Controller boards. Many of these parts have links pointed to corresponding data sheets copied from the chip manufacturer sites( Xilinx, National, Texas Instruments, Data Delay Lines), so if in future any questions will arise these sheets will provide relevant to the production time information. In order to view these datasheets you need Acrobat Reader.
 
Description Count Geometry
Xilinx4013  1 pq-160
mc10124  1 dip16
mc10125  2 dip16
ds96174  4 dip16
ds96175  4 dip16
ds96176CN  2 dip8
74als520N Octal binary and BCD identity comparators with enable  1 dip20
74als645a-1 Octal bus transceiver 2 dip20
74ls04N HEX inverters 1 dip14
74ls32N Quad 2-input positive OR gates 1 dip14
74ls244N  Octal buffers and line drivers 2 dip20
74ls541N Octal buffers and line drivers 2 dip20
idt7204 2 dip28
PDU-15F-6  1 dip24s
34conn 2
16conn 1
8conn 1
VMEconn 1
LED 6
switch_3 1 dip6
2n3904  6 t092
mc7905act  1 to220
oscill 60 MHz 1
.1uf capacitor 44 .1inch
33uf capacitor 4 .3inch
fuse 3A 1 .4inch
fuse 1A 1 .4inch
jumper 4
resistors bussed 10 (510 Ohm) 2 sip10
resistors bussed 10 (390 Ohm) 1 sip10
resistors puldown 8 (120 Ohm) 8 sip8
resistors puldown 8 (100 Ohm) 2 sip8
resistor 4.7k 9 .3inch
resistor 200 7 .3inch
resistor 120 2 .3inch
 

Power dissipation:

Vcc +5V:
 
Chip Quantity Current, mA Total Current, mA
ds96174 4 60 240
ds96175 4 60 240
ds96176 2 40 240
LED 6 25 125
idt7204 2
Xilinx4013 1 10 10
74als520a-1
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