To minimize the capacitive loading of the global clock (GCLK) signal, four separate, but identical, clock lines are used to distribute GCLK within the RPC readout crates. These signals are labeled GCLK0, GCLK1, GCLK2, and GCLK3. This allows one to use the highest possible clock speed, minimizing the deadtime of the TMUX scheme.
Most production boards (V2.1a) have an input buffer chip, so that each board adds just a single CMOS load to its clock line. The clock line to be used by a particular board is determined by an on-board jumper.
The first (approx.) 64 boards (V2.1) did not have this buffer and therefore present four CMOS loads to GCLK0, to which the are hardwired (i.e., they have no jumper). The situation is illustrated in this figure.